PHY2060

Active Equaliser and Retimer

The PHY2060 is an advanced serial retiming receiver designed to operate at the 10 Gigabit Ethernet data rate of 10.3125Gbps. Low power dissipation and a small package outline makes the PHY2060 ideally suited for small form factor modules such as XFP and SFP as well as mounting on host boards using linear SFP+ modules.

The PHY2060 integrates a high performance clock recovery circuit and an adaptive equaliser circuit which compensates for inter-symbol interference (ISI), increasing fiber and copper transmission distances.

The PHY2060 consumes a typical power of 0.95W and is packaged in a 5mm x 5mm FCBGA with 0.8mm ball pitch.

Key features

• Optimized for 10G Ethernet
• Automatic adaptation of Equaliser with robust built-in algorithms
• Integrated PRBS & BERT
• Loss of Signal (LOS) & Loss of Lock (LOL) alarms
• Selectable 2-wire or SPI microcontroller interface
• Typical power dissipation 0.95W
• Miniature 36pin, 5mm x 5mm, flip-chip BGA package
• High Immunity to dynamic stressors
• Miniature 5 x 5 mm Ball Grid Array (BGA) IC package

Applications

• Optical EDC-enabled receivers e.g. 10GBASE-LRM
• Replaces Rx retimer in Optical XFP applications
• Twin-ax copper cable assemblies up to 30m
• X2, XFP and SFP+ MSAs